Astera Labs is seeking an ASIC Design Student to join their strategic R&D center in Israel. This role involves developing micro-architecture and RTL coding for complex digital blocks powering AI infrastructure. Candidates must be pursuing a degree in Electrical or Computer Engineering with strong logic design skills.
Astera Labs is seeking a Design Verification Student to join their strategic R&D center in Israel. This role involves building SystemVerilog/UVM-based testbenches and verifying high-performance digital blocks for AI infrastructure. Candidates must be pursuing a degree in Electrical or Computer Engineering and work onsite at least 2 days a week.
Astera Labs is establishing a strategic R&D center in Israel and seeking a Physical Design CAD Lead to build local engineering capabilities. The role involves designing automated flows for Synthesis, Place & Route, and Floor-planning while supporting the PD team in optimizing Power, Performance, and Timing. Candidates need expertise in Tcl, Python, and back-end industrial tool suites like Synopsys Fusion Compiler or Cadence Genus.
Astera Labs is seeking a Physical Design Engineer to join their new R&D center in Israel. The role involves leading physical implementation, signoff, and methodology development for AI infrastructure semiconductor chips. Candidates should have experience with RTL2GDS flows and advanced process technologies.
Astera Labs is seeking a Staff/Principal Design Engineer to establish a strategic R&D center in Israel. This role involves designing complex semiconductor chips and digital blocks for AI infrastructure connectivity. Candidates will own the journey from high-level definition through RTL implementation and backend support.
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